- “An Energy-Efficient Generic Accuracy Configurable Multiplier Based on Block-Level Voltage Overscaling,” accepted in IEEE Transactions on Emerging Topics in Computing (Q1, IF=6.595) , May. 2023.
- “X-Rel: Energy-Efficient and Low-Overhead Approximate Reliability Framework for Error-Tolerant Applications Deployed in Critical Systems,” accepted in IEEE Transactions on Very Large Scale Integration Systems , Apr. 2023. DOI: 10.1109/TVLSI.2023.3272226
- “Accurate and Compact Approximate 4:2 Compressors with GDI Structure,” accepted in Circuits, Systems, and Signal Processing (CSSP) , Jan. 2023.
- “BEAD: Bounded Error Approximate Adder with Carry and Sum Speculations,” accepted in Integration, the VLSI journal , Oct. 2022. https://doi.org/10.1016/j.vlsi.2022.10.015
- “Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode,” in ACM Transactions on Design Automation of Electronic Systems (TODAES) , july. 2022. https://doi.org/10.1145/3549936
- “X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 39, no. 10, pp. 2558-2571, Oct. 2020, doi: 10.1109/TCAD.2019.2937738.
- “Block-Based Carry Speculative Approximate Adder for Energy-Efficient Applications,” in IEEE Transactions on Circuits and Systems II: , Express Briefs, vol. 67, no. 1, pp. 137-141, Jan. 2020, doi: 10.1109/TCSII.2019.2901060.
- “PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture,” 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 413-418, doi: 10.23919/DATE.2018.8342045
- “Energy and Reliability Improvement of Voltage-Based, Clustered, Coarse- Grain Reconfigurable Architectures by Employing Quality-Aware Mapping,” in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 3, pp. 480-493, Sept. 2018, doi: 10.1109/JETCAS.2018.2856838.
- “Toward Approximate Computing for Coarse-Grained Reconfigurable Architectures,” in IEEE Micro, vol. 38, no. 6, pp. 63-72, 1 Nov.-Dec. 2018, doi: 10.1109/MM.2018.2873951.
- “Energy Consumption and Lifetime Improvement of Coarse-Grained Reconfigurable Architectures Targeting Low-Power Error-Tolerant Applications”, Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018. Available: 10.1145/3194554.3194631.
- “Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, pp. 1352-1361, April 2017, doi: 10.1109/TVLSI.2016.2643003
- “RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 8, pp. 1089-1093, Aug. 2018, doi: 10.1109/TCSII.2016.2633307.
- “Hybrid redundancy approach to increase the reliability of FPGA based speed controller core for high speed train”, Journal of Electronics (China), vol. 31, no. 3, pp. 256-266, 2014. Available: 10.1007/s11767-014-4011-z.
- “Recent advances in the automated control system of high-speed trains”, 2nd International Conference on Recent Advances in Railway Engineering (ICRARE), Iran University, of Science and Technology, Tehran, Iran.
- “A speed controller system based on FPGA for high speed train”, 2nd International Conference on Recent Advances in Railway Engineering (ICRARE), Iran University of Science and Technology, Tehran, Iran. , April 30–May 1, 2013, 1–7.
Computer Architecture and Dependable Systems Laboratory